PLDs are a well-known type of IC that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to Input/Output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
As discussed above, PLDs may provide a plurality of circuit topologies, whereby reconfigurable digital logic may coexist with high-speed analog circuitry to form a hybrid PLD implementation. In particular, certain PLDs may provide architectures that include MGTs along various columns of the PLD in order to support multi-channel, serial communications.
Implementing such hybrid implementations, however, presents some manufacturing challenges. In particular, while the reconfigurable portion of the PLD, i.e., the fabric, may achieve production yields in the, e.g., 90% range, the production yield of the high-speed analog circuitry may not be as high. Using current topologies, even if only a single MGT on a particular PLD is determined to be defective, then the entire PLD must be scrapped. Further, if the determination that the MGT is defective is not made until after packaging, then the economic loss sustained from scrapping the device is maximized, since most of the expenses associated with producing the PLD, e.g., wafer fabrication and packaging, have already been incurred. Efforts continue, therefore, to increase the yield of these hybrid ICs so as to reduce yield based economic losses.